The present disclosure relates generally to packaging of integrated circuit devices and more particularly to localizing underfill.
Semiconductor devices, such as memory devices, processors, application-specific integrated circuits (ASICs), and other chips are typically fabricated in a multi-step process. A large number of devices are initially fabricated on a large substrate, such as a wafer. The substrate typically includes at least one layer of a semiconductor material, such as silicon, gallium arsenide, and/or the like. Using various photolithographic, depositing, etching, and/or other semiconductor processes, patterns of one or more layers of semiconductor, metals, dielectrics, and/or the like are formed on the substrate to create various devices, interconnects, and so forth. Multiple semiconductor circuits are typically fabricated on each substrate with the substrate being sliced or cut into separate dies or dice, with each of the dies having a circuit or circuits for a specific purpose.
Given the generally small size of the dies, each of the dies is typically mounted onto an interposer or other packaging substrate. The interposer may serve one or more purposes in a package such as providing ease of handling, protecting the die, increasing spacing between contacts on the die to support inclusion of the die in larger circuits, and/or the like. In some cases, multiple dies of the same or different types are mounted on the same interposer so that the interposer may provide packaging support for each of the multiple dies. As part of the mounting processes, an underfill material, such as an epoxy resin, is often used between the dies and the interposer to protect the contacts between the dies and the interposer, to help adhere the dies to the interposer, and/or the like. While underfill may simplify some issues associated with device fabrication, but it may also introduce others.
Accordingly, it would be desirable to have improved methods for using underfill during semiconductor packaging.